Since Oct. 2018, she has joined to IDEA lab at the University of Sassari as a postdoctoral researcher. She was a researcher in the Design, Verification and Debugging of Embedded Systems (DVDES) Lab of University of Tehran from 2012 to Sep. 2018. She received the B.Sc. and M.Sc. degrees in Electrical and Computer Engineering Department from Shahid Beheshti University, Tehran, Iran, in 2006 and 2009, respectively, and completed her Ph.D. at School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Tehran, Iran.
High level precision optimization and verification of Embedded Systems, Quantization noise, Approximate computing, Design Automation, Parallel Computing and systems, Machine learning, Computer architecture, Systematic Cell design, Energy-efficient VLSI Circuit Design.
1. M. Grailoo, B. Alizadeh, and B. Forouzandeh, Improved Range Analysis in Fixed-point Polynomial Datapath, in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems (TCAD), 2017 (to appear).
2. M. Grailoo, B. Alizadeh, and B. Forouzandeh, UAFEA: Unified Analytical Framework for IA/AA-based Error Analysis of Fixed-point Polynomial Specifications, in IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 63, no. 10, pp. 994-998, Oct. 2016.
3. T. Nikoubin, M. Grailoo, C. Li, “Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology,” in IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 24, no.1, pp.398-402, 2015.
4. M. Grailoo, M. Hashemi, K. Haghshenas, S. Rezaee, S. Rapolu and T. Nikoubin, “CNTFET Full-Adders for Energy-Efficient Arithmetic Applications,” 2015 6th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Denton, TX, 2015.
5. M. Grailoo, A. Joshi, M. Mulkalapally, T. Nikoubin, “Power and Energy Efficient Standard Cells with CDM Logic Style for Optimization of Multiplier Structures,” in Proceedings of the 7th International Conference on Computing Communication and Networking Technologies, ACM, pp. 10, July 2016.
6. T. Nikoubin, M. Grailoo, “Cell design methodology (CDM) for balanced Carry–InverseCarry circuits in hybrid-CMOS logic style,” Journal of Low Power Electronics [ISSN 1546-1998], pp. 1-18, 2013.
7. T. Nikoubin, M. Grailoo, H. Mozafari, “Cell Design Methodology based on Transmission Gate for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic Style,” Journal of Low Power Electronics [ISSN 1546-1998], American Scientific Publishers, vol. 6, pp. 1–10, July 2010 .
8. M. Grailoo, T. Nikoubin, K. Navi, “Energy Consumption Optimization for Basic Arithmetic Circuits with Transistor Sizing Based on Genetic Algorithm,” International Journal of Recent Trends in Engineering [ISSN 1797-9617] by the Academy Publishers, Finland, IJJCE 2009.
9. M. Grailoo, S. Timarchi, K. Navi, M. Grailoo, “Origami and Cryptography Algorithms,” CSICC. Faculty of Electrical and Computer Engineering, SBU, Tehran, Iran February 20-22, 2007.
10. M. Grailoo, M. Grailoo, A. Bakhshi, “Solving Systems of Nonlinear Equations with an Improved Particle Swarm Optimization,” 4th IEEE International Conference on Computer Science and Information Technology, At Singapore, 2011.