Francesca Palumbo
Assistant Professor
fpalumbo@uniss.it
About Me

She is currently an assistant professor at the University of Sassari, within the Information Engineering unit of the Department of Political Sciences, Communication Sciences and Information Engineering.
She received her summa cum laude “Laurea Degree” in Electronic Engineering in 2005 at the University of Cagliari, then attended the Master Advanced in Embedded System Design in 2006 at the Advanced Learning and Research Institute of the University of Lugano before starting her Ph.D. in Electronic and Computer Engineering at the University of Cagliari.
Her research focus is related to reconfigurable systems and to code generation tools and design automation strategies for advanced reconfigurable hardware architectures. For her studies in the fields of dataflow-based programming and hardware customization, she received two Best Paper Awards at the Conference on Design and Architectures for Signal and Image Processing, respectively in 2011 and in 2015, with the works entitled “The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer” and “MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation”. Dr. Palumbo serves in several different Technical Committee of international conferences and she is a permanent Steering Committee Member of the ACM Conference on Computing Frontiers and Associate Editor of the Springer Journal of Signal Processing Systems.
At the moment, Dr. Palumbo is the scientific coordinator of the CERBERO (ID: 732105) H2020 European Project on Smart Cyber Physical System Design.

Research Interests

Dataflow, Reconfigurable Systems, Low-power, Network on chip, VLSI

Publications

2017

Palumbo, Francesca; Sau, Carlo; Fanni, Tiziana; Raffo, Luigi

Challenging CPS Trade-Off Adaptivity with Coarse-Grained Reconfiguration Conference

2017.

Abstract | Links | BibTeX

Palumbo, Francesca; Rubattu, Claudio; Sau, Carlo; Fanni, Tiziana; Meloni, Paolo; Raffo, Luigi

Dynamic Trade-Off Management for CPS Miscellaneous

2017.

Abstract | Links | BibTeX

Palumbo, Francesca; Sau, Carlo; Meloni, Paolo; Raffo, Luigi

Coarse-Grained Reconfiguration: Run-time Adaptivityin Cyber Physical Systems Miscellaneous

2017.

Abstract | Links | BibTeX

Sau, Carlo; Palumbo, Francesca; Pelcat, Maxime; Heulot, Julien; Nogues, Erwan; Menard, Daniel; Meloni, Paolo; Raffo, Luigi

Challenging the Best HEVC Fractional Pixel FPGA Interpolators with Reconfigurable and Multi-frequency Approximate Computing Journal Article

IEEE Embedded Systems Letters, 9 (3), pp. 65-68, 2017, ISSN: 1943-0663.

Abstract | Links | BibTeX

Masin, M; Palumbo, F; Myrhaug, H; de Filho, Oliveira J A; Pastena, M; Pelcat, M; Raffo, L; Regazzoni, F; Sanchez, A A; Toffetti, A; de la Torre, E; Zedda, K

Cross-layer Design of Reconfigurable Cyber-Physical Systems Conference

IEEE, 2017, ISSN: 1558-1101.

Abstract | Links | BibTeX

Sau, C; Palumbo, F; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, P; Raffo, L

Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing Journal Article

IEEE Embedded Systems Letters, 9 (3), pp. 65-68, 2017.

Abstract | Links | BibTeX

Abdali, E M; Pelcat, M; Berry, F; Diguet, J -P; Palumbo, F

Exploring the performance of partially reconfigurable point-to-point interconnects Conference

2017.

Abstract | Links | BibTeX

Fanni, T; Li, L; Viitanen, T; Sau, C; Xie, R; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, S S

Hardware design methodology using lightweight dataflow and its integration with low power techniques Journal Article

Journal of Systems Architecture, 78 , pp. 15-29, 2017.

Abstract | Links | BibTeX

Palumbo, F; Sau, C; Pani, D; Meloni, P; Raffo, L

Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture Conference

2017.

Abstract | Links | BibTeX

Becchi, M; Palumbo, F

Message from the Program Chairs Conference

2017.

Links | BibTeX

Masin, M; Palumbo, F; Myrhaug, H; Filho, De Oliveira J A; Pastena, M; Pelcat, M; Raffo, L; Regazzoni, F; Sanchez, A A; Toffetti, A; Torre, De La E; Zedda, K

Cross-layer design of reconfigurable cyber-physical systems Conference

2017.

Abstract | Links | BibTeX

Meloni, P; Rubattu, C; Tuveri, G; Pani, D; Raffo, L; Palumbo, F

Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs Journal Article

Journal of Systems Architecture, 76 , pp. 89-101, 2017.

Abstract | Links | BibTeX

Palumbo, F; Fanni, T; Sau, C; Meloni, P

Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy Journal Article

Journal of Signal Processing Systems, 87 (1), pp. 81-106, 2017.

Abstract | Links | BibTeX

Pani, D; Meloni, P; Tuveri, G; Palumbo, F; Massobrio, P; Raffo, L

An FPGA platform for real-time simulation of spiking neuronal networks Journal Article

Frontiers in Neuroscience, 11 , 2017.

Abstract | Links | BibTeX

Sau, C; Fanni, T; Meloni, P; Raffo, L; Pelcat, M; Palumbo, F

Demo: Reconfigurable Platform Composer Tool Conference

2017.

Abstract | Links | BibTeX

Li, L; Fanni, T; Viitanen, T; Xie, R; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, S S

Low power design methodology for signal processing systems using lightweight dataflow techniques Conference

2017.

Abstract | Links | BibTeX

2016

Palumbo, F; Sau, C; Fanni, T; Meloni, P; Raffo, L

SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract Conference

2016.

Abstract | Links | BibTeX

Tuveri, G; Meloni, P; Palumbo, F; Seu, Pietro G; Loi, I; Conti, F; Raffo, L

On-the-fly adaptivity for process networks over shared-memory platforms Journal Article

Microprocessors and Microsystems, 46 , pp. 240-254, 2016.

Abstract | Links | BibTeX

Sau, C; Meloni, P; Raffo, L; Palumbo, F; Bezati, E; Casale-Brunet, S; Mattavelli, M

Automated Design Flow for Multi-Functional Dataflow-Based Platforms Journal Article

Journal of Signal Processing Systems, 85 (1), pp. 143-165, 2016.

Abstract | Links | BibTeX

Fanni, T; Sau, C; Meloni, P; Raffo, L; Palumbo, F

Power and clock gating modelling in coarse grained reconfigurable systems Conference

2016.

Abstract | Links | BibTeX

Banik, S; Bogdanov, A; Fanni, T; Sau, C; Raffo, L; Palumbo, F; Regazzoni, F

Adaptable AES implementation with power-gating support Conference

2016.

Abstract | Links | BibTeX

Sau, C; Carta, N; Raffo, L; Palumbo, F

Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design Journal Article

Journal of Signal Processing Systems, 82 (3), pp. 311-329, 2016.

Abstract | Links | BibTeX

Sau, C; Fanni, L; Meloni, P; Raffo, L; Palumbo, F

Reconfigurable coprocessors synthesis in the MPEG-RVC domain Conference

2016.

Abstract | Links | BibTeX

Fanni, T; Sau, C; Meloni, P; Raffo, L; Palumbo, F

Power modelling for saving strategies in coarse grained reconfigurable systems Conference

2016.

Abstract | Links | BibTeX

Palumbo, F; Fanni, T; Sau, C; Meloni, P; Raffo, L

Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures Journal Article

Journal of Electrical and Computer Engineering, 2016 , 2016.

Abstract | Links | BibTeX

Meloni, P; Palumbo, F; Rubattu, C; Tuveri, G; Pani, D; Raffo, L

MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation Journal Article

Microprocessors and Microsystems, 43 , pp. 67-80, 2016.

Abstract | Links | BibTeX

Palumbo, F; Sau, C; Evangelista, D; Meloni, P; Pelcat, M; Raffo, L

Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC Journal Article

IFAC-PapersOnLine, 49 (25), pp. 145-152, 2016.

Abstract | Links | BibTeX