Francesca Palumbo
Assistant Professor
fpalumbo@uniss.it
About Me

She is currently an assistant professor at the University of Sassari, within the Information Engineering unit of the Department of Political Sciences, Communication Sciences and Information Engineering.
She received her summa cum laude “Laurea Degree” in Electronic Engineering in 2005 at the University of Cagliari, then attended the Master Advanced in Embedded System Design in 2006 at the Advanced Learning and Research Institute of the University of Lugano before starting her Ph.D. in Electronic and Computer Engineering at the University of Cagliari.
Her research focus is related to reconfigurable systems and to code generation tools and design automation strategies for advanced reconfigurable hardware architectures. For her studies in the fields of dataflow-based programming and hardware customization, she received two Best Paper Awards at the Conference on Design and Architectures for Signal and Image Processing, respectively in 2011 and in 2015, with the works entitled “The Multi-Dataflow Composer tool: A runtime reconfigurable HDL platform composer” and “MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation”. Dr. Palumbo serves in several different Technical Committee of international conferences and she is a permanent Steering Committee Member of the ACM Conference on Computing Frontiers and Associate Editor of the Springer Journal of Signal Processing Systems.
At the moment, Dr. Palumbo is the scientific coordinator of the CERBERO (ID: 732105) H2020 European Project on Smart Cyber Physical System Design.

Research Interests

Dataflow, Reconfigurable Systems, Low-power, Network on chip, VLSI

Publications
67 entries « 1 of 2 »

2019

Palumbo, F; Fanni, T; Sau, C; Pulina, L; Raffo, L; Masin, M; Shindin, E; Rojas, P S D; Desnos, K; Pelcat, M; Rodríguez, A; Juárez, E; Regazzoni, F; Meloni, G; Zedda, K; Myrhaug, H; Kaliciak, L; Andriaanse, J; Filho, J O; Munõz, P; Toffetti, A

CERBERO: Cross-layer modEl-based fRamework for multi-oBjective dEsign of Reconfigurable systems in unceRtain hybRid envirOnments Conference

Association for Computing Machinery, Inc, 2019.

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Ferreira, J C; Palumbo, F

Preface to the Special Issue on Methods, Tools, and Architectures for Signal and Image Processing Journal Article

Journal of Signal Processing Systems, 91 (7), pp. 701-702, 2019.

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Palumbo, F

Message from the General Chairs Conference

Association for Computing Machinery, Inc, 2019.

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Nasser, Y; Sau, C; Prévotet, J -C; Fanni, T; Palumbo, F; Hélard, M; Raffo, L

Neu Pow: Artificial Neural Networks for Power and Behavioral Modeling of Arithmetic Components in 45nm ASICs Technology Conference

Association for Computing Machinery, Inc, 2019.

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Al-Ars, Z; Basten, T; Beer, A; Geilen, M; Goswami, D; Jaäskelaïnen, P; Kadlec, J; Alejandro, M M; Palumbo, F; Peeren, G; Pomante, L; Linden, F V; Saarinen, J; Säntti, T; Sau, C; Zedda, M K

The FitOptiVis ECSEL Project: Highly Efficient Distributed Embedded Image/Video Processing in Cyber-Physical Systems Invited Pape Conference

Association for Computing Machinery, Inc, 2019.

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Meloni, P; Loi, D; Busia, P; Deriu, G; Pimentel, A D; Sapra, D; Stefanov, T; Minakova, S; Conti, F; Benini, L; Pintor, M; Biggio, B; Moser, B; Shepelev, N; Fragoulis, N; Theodorakopoulos, I; Masin, M; Palumbo, F

Optimization and deployment of CNNs at the Edge: The ALOHA experience Conference

Association for Computing Machinery, Inc, 2019.

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Palumbo, F; Becchi, M

Editorial: Special Issue on Computing Frontiers Journal Article

Journal of Signal Processing Systems, 91 (3-4), pp. 273, 2019.

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Fanni, T; Rodriguez, A; Sau, C; Suriano, L; Palumbo, F; Raffo, L; Torre, E D L

Multi-grain reconfiguration for advanced adaptivity in cyber-physical systems Conference

Institute of Electrical and Electronics Engineers Inc., 2019.

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Li, L; Sau, C; Fanni, T; Li, J; Viitanen, T; Christophe, F; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, S S

An integrated hardware/software design methodology for signal processing systems Journal Article

Journal of Systems Architecture, 93 , pp. 1-19, 2019.

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Palumbo, F; Sau, C; Fanni, T; Raffo, L

Challenging CPS trade-off adaptivity with coarse-grained reconfiguration Journal Article

Lecture Notes in Electrical Engineering, 512 , pp. 57-63, 2019.

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Fanni, L; Suriano, L; Rubattu, C; de Rojas, P S; de la Torre, E; Palumbo, F

A dataflow implementation of inverse kinematics on reconfigurable heterogeneous MPSoC Conference

2457 , CEUR-WS, 2019.

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Masin, M; Palumbo, F; Adriaanse, J; Myrhaug, H; Regazzoni, F; Sanchez, M; Zedda, K

Elicitation of technical requirements in large research projects: The CERBERO approach Conference

Part F147772 , Association for Computing Machinery, 2019.

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Palumbo, F; Fanni, T; Sau, C; Rodríguez, A; Madroñal, D; Desnos, K; Morvan, A; Pelcat, M; Rubattu, C; Lazcano, R; Raffo, L; de la Torre, E; Juárez, E; Sanz, C; de Rojas, Sánchez P

Hardware/Software self-adaptation in CPS: The CERBERO project approach Journal Article

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 11733 LNCS , pp. 416-428, 2019.

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2018

Palumbo, F; Pilato, C; Pulina, L; Sau, C

Preface Conference

2208 , CEUR-WS, 2018.

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Desnos, K; Palumbo, F

Dataflow modeling for reconfigurable signal processing systems Book

Springer International Publishing, 2018.

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Meloni, P; Loi, D; Deriu, G; Ripolles, O; Solans, D; Pimentel, A D; Sapra, D; Pintor, M; Biggio, B; Moser, B; Shepeleva, N; Stefanov, T; Minakova, S; Conti, F; Benini, L; Fragoulis, N; Theodorakopoulos, I; Masin, M; Palumbo, F

ALOHA: An architectural-aware framework for deep learning at the edge Conference

Association for Computing Machinery, 2018.

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Meloni, P; Loi, D; Deriu, G; Pimentel, A D; Saprat, D; Pintort, M; Biggio, B; Ripolles, O; Solans, D; Conti, F; Benini, L; Stefanov, T; Minakova, S; Moser, B; Shepeleva, N; Masin, M; Palumbo, F; Fragoulis, N; Theodorakopoulos, I

Architecture-aware design and implementation of CNN algorithms for embedded inference: The ALOHA project Conference

2018-December , Institute of Electrical and Electronics Engineers Inc., 2018.

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Rubattu, C; Palumbo, F; Pelcat, M

Adaptive software-augmented hardware reconfiguration with dataflow design automation Conference

2018-January , Institute of Electrical and Electronics Engineers Inc., 2018.

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Palumbo, F; Pilato, C; Pulina, L; Sau, C

Preface Conference

2208 , CEUR-WS, 2018.

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Rubattu, C; Palumbo, F; Sau, C; Salvador, R; Serot, J; Desnos, K; Raffo, L; Pelcat, M

Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators Journal Article

IEEE Embedded Systems Letters, 2018.

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2017

Sau, C; Palumbo, F; Pelcat, M; Heulot, J; Nogues, E; Menard, D; Meloni, P; Raffo, L

Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing Journal Article

IEEE Embedded Systems Letters, 9 (3), pp. 65-68, 2017.

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Abdali, E M; Pelcat, M; Berry, F; Diguet, J -P; Palumbo, F

Exploring the performance of partially reconfigurable point-to-point interconnects Conference

Institute of Electrical and Electronics Engineers Inc., 2017.

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Fanni, T; Li, L; Viitanen, T; Sau, C; Xie, R; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, S S

Hardware design methodology using lightweight dataflow and its integration with low power techniques Journal Article

Journal of Systems Architecture, 78 , pp. 15-29, 2017.

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Palumbo, F; Sau, C; Pani, D; Meloni, P; Raffo, L

Feasibility study of real-time spiking neural network simulations on a swarm intelligence based digital architecture Conference

Institute of Electrical and Electronics Engineers Inc., 2017.

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Becchi, M; Palumbo, F

Message from the Program Chairs Conference

Association for Computing Machinery, Inc, 2017.

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Masin, M; Palumbo, F; Myrhaug, H; Filho, De Oliveira J A; Pastena, M; Pelcat, M; Raffo, L; Regazzoni, F; Sanchez, A A; Toffetti, A; Torre, De La E; Zedda, K

Cross-layer design of reconfigurable cyber-physical systems Conference

Institute of Electrical and Electronics Engineers Inc., 2017.

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Meloni, P; Rubattu, C; Tuveri, G; Pani, D; Raffo, L; Palumbo, F

Real-Time neural signal decoding on heterogeneous MPSocs based on VLIW ASIPs Journal Article

Journal of Systems Architecture, 76 , pp. 89-101, 2017.

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Palumbo, F; Fanni, T; Sau, C; Meloni, P

Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy Journal Article

Journal of Signal Processing Systems, 87 (1), pp. 81-106, 2017.

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Pani, D; Meloni, P; Tuveri, G; Palumbo, F; Massobrio, P; Raffo, L

An FPGA platform for real-time simulation of spiking neuronal networks Journal Article

Frontiers in Neuroscience, 11 , 2017.

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Montanari, A; Palumbo, F; Vichi, M

Preface Conference

(195089), Springer Berlin Heidelberg, 2017.

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2016

Palumbo, F; Sau, C; Fanni, T; Meloni, P; Raffo, L

SS-design: Dataflow-based design of coarse-grained: Reconfigurable platforms reconfigurable platform composer tool project - Extended abstract Conference

Institute of Electrical and Electronics Engineers Inc., 2016.

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Tuveri, G; Meloni, P; Palumbo, F; Seu, Pietro G; Loi, I; Conti, F; Raffo, L

On-the-fly adaptivity for process networks over shared-memory platforms Journal Article

Microprocessors and Microsystems, 46 , pp. 240-254, 2016.

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Sau, C; Meloni, P; Raffo, L; Palumbo, F; Bezati, E; Casale-Brunet, S; Mattavelli, M

Automated Design Flow for Multi-Functional Dataflow-Based Platforms Journal Article

Journal of Signal Processing Systems, 85 (1), pp. 143-165, 2016.

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Sau, C; Fanni, T; Meloni, P; Raffo, L; Pelcat, M; Palumbo, F

Demo: Reconfigurable Platform Composer Tool Conference

0 , IEEE Computer Society, 2016.

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Li, L; Fanni, T; Viitanen, T; Xie, R; Palumbo, F; Raffo, L; Huttunen, H; Takala, J; Bhattacharyya, S S

Low power design methodology for signal processing systems using lightweight dataflow techniques Conference

0 , IEEE Computer Society, 2016.

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Palumbo, F; Pelcat, M; Menard, D

Introduction to the 2nd workshop on design of low Power EMbedded Systems Conference

Association for Computing Machinery, Inc, 2016.

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Fanni, T; Sau, C; Meloni, P; Raffo, L; Palumbo, F

Power and clock gating modelling in coarse grained reconfigurable systems Conference

Association for Computing Machinery, Inc, 2016.

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Banik, S; Bogdanov, A; Fanni, T; Sau, C; Raffo, L; Palumbo, F; Regazzoni, F

Adaptable AES implementation with power-gating support Conference

Association for Computing Machinery, Inc, 2016.

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Sau, C; Carta, N; Raffo, L; Palumbo, F

Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design Journal Article

Journal of Signal Processing Systems, 82 (3), pp. 311-329, 2016.

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Sau, C; Fanni, L; Meloni, P; Raffo, L; Palumbo, F

Reconfigurable coprocessors synthesis in the MPEG-RVC domain Conference

Institute of Electrical and Electronics Engineers Inc., 2016.

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Fanni, T; Sau, C; Meloni, P; Raffo, L; Palumbo, F

Power modelling for saving strategies in coarse grained reconfigurable systems Conference

Institute of Electrical and Electronics Engineers Inc., 2016.

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Palumbo, F; Fanni, T; Sau, C; Meloni, P; Raffo, L

Modelling and automated implementation of optimal power saving strategies in coarse-grained reconfigurable architectures Journal Article

Journal of Electrical and Computer Engineering, 2016 , 2016.

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Palumbo, F; Sau, C; Evangelista, D; Meloni, P; Pelcat, M; Raffo, L

Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC Journal Article

IFAC-PapersOnLine, 49 (25), pp. 145-152, 2016.

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Meloni, P; Palumbo, F; Rubattu, C; Tuveri, G; Pani, D; Raffo, L

MPSoCs for real-time neural signal decoding: A low-power ASIP-based implementation Journal Article

Microprocessors and Microsystems, 43 , pp. 67-80, 2016.

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2015

Meloni, P; Tuveri, G; Pani, D; Raffo, L; Palumbo, F

Exploring custom heterogeneous MPSoCs for real-Time neural signal decoding Conference

2015-December , IEEE Computer Society, 2015.

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Pani, D; Sau, C; Palumbo, F; Raffo, L

Computing swarms for self-adaptiveness and self-organizationin floating-point array processing Journal Article

ACM Transactions on Autonomous and Adaptive Systems, 10 (3), 2015.

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Sau, C; Palumbo, F

Automatic generation of dataflow-based reconfigurable co-processing units Conference

2015-May , IEEE Computer Society, 2015.

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Fanni, T; Sau, C; Raffo, L; Palumbo, F

Automated power gating methodology for dataflow-based reconfigurable systems Conference

Association for Computing Machinery, Inc, 2015.

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Palumbo, F; Sau, C; Raffo, L

Coarse-grained reconfiguration: Dataflow-based power management Journal Article

IET Computers and Digital Techniques, 9 (1), pp. 36-48, 2015.

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2014

Palumbo, F; Sau, C; Raffo, L

Power-awarness in coarse-grained reconfigurable designs: A dataflow based strategy Conference

Institute of Electrical and Electronics Engineers Inc., 2014.

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67 entries « 1 of 2 »